Semiconductor Device Failure Analysis - Semiconductor Device Chip Soldering Tips and Control

With the development of technology, the soldering (adhesion) techniques of chips have also become more and more sophisticated. The failure of soldering (adhesion) of semiconductor devices is mainly related to poor cleanliness, unevenness, oxides, improper heating, and substrate plating quality. The resin paste method is also constrained and influenced by the composition of the adhesive and its related physical and mechanical properties. To solve the problem of poor micro soldering, we must understand the mechanics of different techniques, analyze various failure modes one by one, and promptly identify the adverse factors affecting the quality of soldering (adhesion). At the same time, we strictly test the production process and strengthen process management to effectively avoid Potential damage to device reliability due to bad die soldering.

This article first introduced the chip welding (paste) skills and mechanisms, followed by the introduction of the failure mode analysis, the final introduction of the welding quality of the three inspection techniques and welding causes and corresponding countermeasures, follow the specific small series together to find out.

Soldering of a chip refers to the technique of forming a solid, conductive, or insulative connection between the semiconductor chip and the carrier (package housing or substrate). In addition to providing mechanical and electrical connections to the device, the solder layer must also provide good heat dissipation for the device. The techniques can be divided into resin bonding methods and metal alloy welding methods.

The resin adhesive method uses a resin adhesive to form an insulating layer between the chip and the package body or to form a good conductor of electricity and heat by doping a metal (such as gold or silver) therein. Most adhesives use epoxy resin. Epoxy resin is a stable linear polymer. After the curing agent is added, the epoxy group is opened to form a hydroxyl group and cross-linked, so that the linear polymer crosslinks into a network structure and solidifies into a thermosetting plastic. The process consists of liquid or viscous liquid → gelling → solid. The curing conditions are mainly determined by the choice of the type of curing agent. The content of the doped metal determines the electrical and thermal conductivity of the product.

Silver-doped epoxy paste is one of the most popular chip-bonding techniques. It requires a low curing temperature, which can avoid thermal stress, but has the disadvantage of silver migration. In recent years, gold conductive adhesives used in small and medium power transistors are superior to silver conductive adhesives. Non-conductive fillers, including alumina, yttria, and magnesia, can be used to improve thermal conductivity. The resin sticking method is widely used due to the fact that the carrier does not need to be heated in the operation process, the equipment is simple, the process automation is easy to realize and the economic benefits are applied, and the application is more extensive in integrated circuits and low power devices. Resin-bonded devices have high thermal resistance and resistance. The resin is simply decomposed at a high temperature, precipitation of the filler may occur, leaving only a layer of resin on the affixed surface to increase the resistance at that location. It is therefore not suitable for devices that require operation at high temperatures or require low paste resistance. In addition, the mechanical strength of the resin-bonded surface is far less than that of eutectic bonding.

The metal alloy welding method mainly refers to gold-silicon, gold-bismuth, gold-tin and other eutectic welding. Herein, the gold-silicon eutectic soldering is mainly discussed as an example. Gold has a melting point of 1063°C and silicon has a melting point of 1414°C, but the melting point of gold-silicon alloys is much lower than that of gold and silicon. From the binary phase diagram, it can be seen that the Eu-Si eutectic eutectic point temperature is 370°C with 31% silicon atoms and 69% gold atoms. This eutectic point is the main basis for selecting the proper welding temperature and controlling the welding depth. The gold-silicon eutectic soldering method is the chip under absolute pressure (with friction or ultrasonic). When the temperature is higher than the eutectic temperature, the gold-silicon-silicide is financialized into liquid Au-Si eutectic; after cooling, when the temperature is low At the eutectic temperature, the eutectic melts from the liquid phase to a mechanical mixture that combines with each other in the form of crystal grains—silicon-silicon eutectic crystals—to completely solidify, creating a solid ohmic contact weld face. The eutectic welding method has the advantages of high mechanical strength, small thermal resistance, good stability, high reliability and containing less impurities, and thus has been widely used in chip assembly of microwave power devices and components and has been highly reliable. The device packaging industry is favored, its welding strength has reached 245MPa [4]. Metal alloy soldering also includes "soft solder" soldering (eg, 95Pb/5Sn, 92.5Pb/5In/2.5Ag) because of its relatively small mechanical strength, which is less commonly used in semiconductor device chip soldering. .

Regardless of which welding technique is used, the sign of success is that the interface between the chip and the solder surface of the package is solid, flat and free of voids. Because Au-Si eutectic soldering is most widely used in semiconductor devices and microelectronic circuits, the reason for the failure of such soldering techniques and the measures for solving them are discussed here.

1, bad ohmic contact

Good ohmic contact between the chip and the substrate is a prerequisite for ensuring the normal operation of the power device. Poor ohmic contact will increase the thermal resistance of the device, uneven heat dissipation, affect the distribution of current in the device, destroy the thermal stability of the device, and even cause the device to burn. The heat dissipation of semiconductor devices includes radiation, convection, and conduction. Among them, heat conduction is the main mode of heat dissipation. Taking a silicon microwave Power Transistor as an example, Fig. 1 shows a silicon microwave power tube assembly model, and Fig. 2 shows its thermal equivalent circuit. Tj is the die junction temperature and TC is the case temperature. R1, R2, R3, R4, and R5 are the thermal resistances of the chip, Au-Si solder layer, BeO, interface solder layer, and tungsten copper base, respectively. The total thermal resistance R = R1 + R2 + R3 + R4 + R5. The heat generated by the chipset is mainly transmitted to the WCu housing through the silicon wafer, solder layer, and BeO. Welds and voids in the Au-Si solder layer are the main cause of poor ohmic contact. The voids can cause current-dense effects, and irreversible and destructive thermoelectric breakdown, ie, secondary breakdown, may occur near the Au-Si solder layer. The poor ohmic contact of the soldering layer brings great potential for device reliability.

2, thermal stress failure

This is a failure caused by mechanical stress. Because the ultimate manifestation of its failure is often a weld face crack or chip delamination, it is discussed here as one of the micro weld failure modes. The welding interface of microelectronic devices is composed of parts of materials with different properties, such as Si, SiO2, BeO, Al2O3, WCu, and the like. The linear thermal expansion coefficient of these materials are different. For example, WCu, which is often used as a base, has a coefficient of expansion that is almost 4 times larger than that of Si crystals. When they are joined together, there are compressive or tensile stresses between different material interfaces. Microwave power devices are often subjected to thermal cycling during operation because the thermal expansion coefficients of the chip and the package are different. During the thermal cycle, periodic shear stress occurs between the soldering surfaces. These stresses may concentrate on the cavity to make the solder. The formation of cracks even cracks the silicon wafer, eventually causing the device to fail due to thermal fatigue.

In the solder layer between the chip and the package, the maximum thermal shear deformation can be estimated as

S=DΔαΔT/2d (1)

In the formula, D is the diagonal dimension of the chip; d is the thickness of the welding layer; ΔT=Tmax-Tmin, Tmax is the temperature of the solidification line of the solder, Tmin is the lowest temperature in the device screening; Δα is the thermal expansion coefficient of the chip and the substrate material. difference.

From the above equation, it can be seen that the thermal deformation is directly proportional to the size of the chip, and the larger the chip size, the greater the shear force that the solder chip undergoes during thermal cycling after soldering. From this perspective, the use of small chip multicellular synthesis for high-power devices is essential.

In soldering, the thermal matching of the chip and the substrate must be fully considered. If a ceramic substrate (such as AlN) having a thermal expansion coefficient close to that of silicon is used in a silicon device, the thermal stress will be greatly reduced and the device can be used for large chip assembly.

1. Shear force measurement

This is the most common and intuitive technique for verifying the quality of soldering between the chip and the substrate. Figure 3 shows the relationship between the minimum shear force and the chip area of the GJB548A-96 used for chip soldering. In the case of good soldering, even if the chip is shattered, there is still a large trace of chip residue at the solder joint. The chip substrate material is not adhered to the general solder cavity, and the size and density of the cavity can be directly observed after the chip is pushed away. Figure 4 is a photograph of the solder void observed after the device chip is pushed off. The devices pasted with the resin paste method are required to measure the shear strength at different temperatures if they are to be operated at high and low temperatures for a long period of time.

2, electrical performance test

For bipolar devices in which the chip is electrically connected to the substrate or substrate (eg, eutectic solder, conductive paste), the quality of soldering (adhesion) directly affects the device's thermal resistance and saturation voltage drop Vces, so the transistor Devices such as these can be used to check the quality of soldering of a chip without loss by measuring the Vces of the device. In the case of ensuring good electrical performance of the chip, if Vces is too large, then the chip may be Weld-weld or have a large "hole." This technique can be used for mass production of online exams.

3, ultrasonic testing

The theoretical basis for ultrasonic testing techniques is that the interfaces of different media have different acoustic properties, and the ability to reflect ultrasound is also different. When the ultrasound encounters a defect, it will reflect back to produce a "shadow" with similar projected area and defects. For devices using multiple layers of metal-ceramic packages, the package must be backside thinned and then tested. At the same time, due to the thermal stress caused by the welding failure, it is difficult to find with general examination and testing methods. It is necessary to apply high stress to the device. Generally, the defect is activated after aging, that is, the device can only be found after the failure. Figure 5 is a photomicrograph of a failed device after thinning on the back side. The inside of the black circle is divided into soldering defects. Ultrasonic can accurately detect the position and size of defects in the welding area.

Using ultrasonic flaw detectors for ultrasonic testing is an effective technique for verifying the quality of chip soldering.

1, the back of the chip oxidation

In the production process of the device, the gold is often vaporized on the back of the chip before welding. At the Au-Si eutectic temperature, Si will penetrate through the gold layer and oxidize to produce SiO 2, which will inhomogeneize the welding infiltration and lead to a decrease in the welding strength. Even at room temperature, silicon atoms slowly move to the surface of the gold layer through interdiffusion between grains. Therefore, the protective gas N2 must ensure sufficient flow during welding, and it is better to add part of H2 for reduction. The preservation of the chip should also be given sufficient attention, not only to pay attention to the temperature and humidity of the environment, but also to consider its future solderability. For long-term unused chips should be stored in a nitrogen cabinet.

2, the welding temperature is too low

Although the Au-Si eutectic point is 370°C, heat must be lost during the transfer process, so a slightly higher portion should be selected, but not too high, so as to avoid oxidation of the surface of the envelope. The welding temperature must also be adjusted according to the material, size, and heat capacity of the package. In order to ensure the welding quality, the surface temperature of the heated susceptor should be measured periodically with a surface thermometer, and the temperature of the welding surface should be monitored if necessary.

3, the pressure is too small or uneven during welding

Absolute pressure should be applied to the chip during soldering. Too little or uneven pressure can create voids or welds between the chip and the substrate. Table 2 compares the shear strength of a certain type of chip under different pressures. From Table 2, it can be seen that after the pressure is reduced, the shear strength of the chip is greatly reduced, and the residual area of the silicon wafer is also less than 50% observed in the experiment. But you can't make too much pressure to avoid debris. Therefore, the adjustment of pressure during welding is very important. It is necessary to adjust according to the comprehensive conditions of the material, thickness, and size of the chip. Accurately accumulating data in practice can achieve ideal welding results.

4, poor substrate cleanliness

Substrate contamination, partial oil or oxidation can seriously affect the wettability of the solder surface. This contamination is relatively simple to observe during the welding process and the substrate must be reprocessed.

5, thermal stress is too large

The failure caused by thermal stress is a slow gradual process, it is not easy to detect, but it is extremely harmful. The larger the general chip thickness, the smaller the stress. So the chip should not be too thin. In addition, if the substrate or base does not match the thermal performance of the chip, it will also cause great mechanical stress. The substrate or base before welding can be preheated at 200°C first, and the tip for picking up the chip can also be properly heated to reduce thermal shock. After welding, it can be cooled slowly under N2 atmosphere, and part of the stress can be eliminated during this cooling process.

6, the substrate gold layer is too thin

When the substrate gold plating layer is thin and not dense enough, even under the protection of nitrogen, when the Au-Si eutectic temperature is reached, the plating layer will undergo severe discoloration, which will affect the welding strength. Experiments have shown that for a 1mm × 1mm chip, the thickness of the gold plating layer on the substrate is greater than 2μm to obtain reliable eutectic soldering. In general, the larger the chip size, the corresponding increase in the gold plating layer.